29.9.2 Clock Unit n Control

Name:	CLKCTRLn
Offset:	0x04 + n*0x04 [n=0..1]
Reset:	0x00000000
Property:	Enable-Protected, PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	MCKOUTINV	SCKOUTINV	FSOUTINV	MCKOUTDIV[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	MCKDIV[4:0]					MCKEN		MCKSEL
Access	R/W	R/W	R/W	R/W	R/W	R/W		R/W
Reset	0	0	0	0	0	0		0


Bit	15	14	13	12	11	10	9	8
				SCKSEL	FSINV			FSSEL
Access				R/W	R/W			R/W
Reset				0	0			0


Bit	7	6	5	4	3	2	1	0
	BITDELAY	FSWIDTH[1:0]		NBSLOTS[2:0]			SLOTSIZE[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – MCKOUTINV Host Clock Output Invert

Value	Description
0	The Host Clock n is output without inversion.
1	The Host Clock n is inverted before being output.

Bit 30 – SCKOUTINV Serial Clock Output Invert

Value	Description
0	The Serial Clock n is output without inversion.
1	The Serial Clock n is inverted before being output.

Bit 29 – FSOUTINV Frame Sync Output Invert

Value	Description
0	The Frame Sync n is output without inversion.
1	The Frame Sync n is inverted before being output.

Bits 28:24 – MCKOUTDIV[4:0] Host Clock Output Division Factor

The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Host Clock n output.

Bits 23:19 – MCKDIV[4:0] Host Clock Division Factor

The Host Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n.

Bit 18 – MCKEN Host Clock Enable

Value	Description
0	The Host Clock n division and output is disabled.
1	The Host Clock n division and output is enabled.

Bit 16 – MCKSEL Host Clock Select

This field selects the source of the Host Clock n.


MCKSEL	Name	Description
0x0	GCLK	GCLK_I2S_n is used as Host Clock n source
0x1	MCKPIN	MCKn input pin is used as Host Clock n source

Bit 12 – SCKSEL Serial Clock Select

This field selects the source of the Serial Clock n.


SCKSEL	Name	Description
0x0	MCKDIV	Divided Host Clock n is used as Serial Clock n source
0x1	SCKPIN	SCKn input pin is used as Serial Clock n source

Bit 11 – FSINV Frame Sync Invert

Value	Description
0	The Frame Sync n is used without inversion.
1	The Frame Sync n is inverted before being used.

Bit 8 – FSSEL Frame Sync Select

This field selects the source of the Frame Sync n.


FSSEL	Name	Description
0x0	SCKDIV	Divided Serial Clock n is used as Frame Sync n source
0x1	FSPIN	FSn input pin is used as Frame Sync n source

Bit 7 – BITDELAY Data Delay from Frame Sync


BITDELAY	Name	Description
0x0	LJ	Left Justified (0 Bit Delay)
0x1	I2S	I2S (1 Bit Delay)

Bits 6:5 – FSWIDTH[1:0] Frame Sync Width

This field selects the duration of the Frame Sync output pulses.

When not in Burst mode, the Clock unit n operates in continuous mode when enabled, with periodic Frame Sync pulses and Data samples.

In Burst mode, a single Data transfer starts at each Frame Sync pulse; these pulses are 1-bit wide and occur only when a Data transfer is requested. Note that the compact stereo modes (16C and 8C) are not supported in the Burst mode.


FSWIDTH[1:0]	Name	Description
0x0	SLOT	Frame Sync Pulse is 1 Slot wide (default for I²S protocol)
0x1	HALF	Frame Sync Pulse is half a Frame wide
0x2	BIT	Frame Sync Pulse is 1 Bit wide
0x3	BURST	Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested