29.9.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SEREN1 | SEREN0 | CKEN1 | CKEN0 | ENABLE | SWRST | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 4, 5 – SERENx Serializer x Enable [x=1..0]
Writing a '0' to this bit will disable the Serializer x.
Writing a '1' to this bit will enable the Serializer x.
| Value | Description |
|---|---|
| 0 | The Serializer x is disabled. |
| 1 | The Serializer x is enabled. |
Bits 2, 3 – CKENx Clock Unit x Enable [x=1..0]
Writing a '0' to this bit will disable the Clock Unit x.
Writing a '1' to this bit will enable the Clock Unit x.
| Value | Description |
|---|---|
| 0 | The Clock Unit x is disabled. |
| 1 | The Clock Unit x is enabled. |
Bit 1 – ENABLE Enable
Writing a '0' to this bit will disable the module.
Writing a '1' to this bit will enable the module.
| Value | Description |
|---|---|
| 0 | The peripheral is disabled. |
| 1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers to their initial state, and the peripheral will be disabled.
Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
The I2S generic clocks must be enabled before triggering Software Reset, hence the logic in all clock domains can be reset.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing. |
| 1 | The reset operation is ongoing. |