32.22.4 Host Status Bank

Original offset 0x0A & 0x1A

Name: STATUS_BK
Offset: 0x0A
Reset: 0xXXXXXXX
Property: NA

Bit 76543210 
       ERRORFLOWCRCERR 
Access R/WR/W 
Reset xx 

Bit 1 – ERRORFLOW Error Flow Status

This bit defines the Error Flow Status.

This bit is set when a Error Flow has been detected during transfer from/towards this bank.

For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition has occurred.

ValueDescription
0 No Error Flow detected.
1 A Error Flow has been detected.

Bit 0 – CRCERR CRC Error

This bit defines the CRC Error Status.

This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.

ValueDescription
0 No CRC Error.
1 CRC Error detected.