41.12.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics

Table 41-46. FDPLL96M Characteristics(1) (Device Variant A / Die revision E)
ParameterConditionsSymbolMin.Typ.Max.Unit
Input frequencyfIN32-2000kHz
Output frequencyfOUT48-96MHz
Current consumptionfIN = 32kHz, fOUT = 48MHzIFDPLL96M-500733μA
fIN = 32kHz, fOUT = 96MHz-9001235
Period jitterfIN = 32kHz, fOUT = 48MHzJp-1.34%
fIN = 32kHz, fOUT = 96MHz-3.17
fIN = 2MHz, fOUT = 48MHz-1.34
fIN = 2MHz, fOUT = 96MHz-3.69
Lock TimeAfter startup, time to get lock signal.

fIN = 32kHz, fOUT = 96MHz

tLOCK-12ms
fIN = 2MHz, fOUT = 96MHz-2550μs
Duty cycleDuty405060%
Table 41-47. FDPLL96M Characteristics(1) (Device Variant B / Die revision F)
ParameterConditionsSymbolMin.Typ.Max.Unit
Input frequencyfIN32-2000kHz
Output frequencyfOUT48-96MHz
Current consumptionfIN = 32kHz, fOUT = 48MHzIFDPLL96M-500-μA
fIN = 32kHz, fOUT = 96MHz-900-
Period jitterfIN = 32kHz, fOUT = 48MHzJp-2.14.0%
fIN = 32kHz, fOUT = 96MHz-4.011.0
fIN = 2MHz, fOUT = 48MHz-2.24.0
fIN = 2MHz, fOUT = 96MHz-4.712.0
Lock TimeAfter startup, time to get lock signal.

fIN = 32kHz, fOUT = 96MHz

tLOCK-1.22ms
fIN = 2MHz, fOUT = 96MHz-2535μs
Duty cycleDuty405060%
  1. All values have been characterized with FILTSEL[1/0] as default value.