39.8.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics

Table 39-47. FDPLL96M Characteristics(1) (Device Variant A)
SymbolParameterConditionsMin.Typ.Max.Units
fINInput frequency32-2000KHz
fOUTOutput frequency48-96MHz
IFDPLL96MCurrent consumptionfIN= 32 kHz, fOUT= 48 MHz-500700μA
fIN= 32 kHz, fOUT= 96 MHz-9001200
JpPeriod jitterfIN= 32 kHz, fOUT= 48 MHz-1.52.0%
fIN= 32 kHz, fOUT= 96 MHz-3.010.0
fIN= 2 MHz, fOUT= 48 MHz-1.32.0
fIN= 2 MHz, fOUT= 96 MHz-3.07.0
tLOCKLock TimeAfter start-up, time to get lock signal.

fIN= 32 kHz, fOUT= 96 MHz

-1.32ms
fIN= 2 MHz, fOUT= 96 MHz-2550μs
DutyDuty cycle405060%
Table 39-48. FDPLL96M Characteristics(1) (Device Variant B and L with Silicon Revision E)
SymbolParameterConditionsMin.Typ.Max.Units
fINInput frequency32-2000KHz
fOUTOutput frequency48-96MHz
IFDPLL96MCurrent consumptionfIN= 32 kHz, fOUT= 48 MHz-500740μA
fIN= 32 kHz, fOUT= 96 MHz-9001262
JpPeriod jitterfIN= 32 kHz, fOUT= 48 MHz-1.52.5%
fIN= 32 kHz, fOUT= 96 MHz-4.010.5
fIN= 2 MHz, fOUT= 48 MHz-1.62.5
fIN= 2 MHz, fOUT= 96 MHz-4.611.0
tLOCKLock TimeAfter start-up, time to get lock signal.

fIN= 32 kHz, fOUT= 96 MHz

-1.22ms
fIN= 2 MHz, fOUT= 96 MHz-2550μs
DutyDuty cycle405060%
Table 39-49. FDPLL96M Characteristics(1) (Device Variant B, C, D and L with Silicon Revision F and G)
SymbolParameterConditionsMin.Typ.Max.Units
fINInput frequency32-2000KHz
fOUTOutput frequency48-96MHz
IFDPLL96MCurrent consumptionfIN= 32 kHz, fOUT= 48 MHz-500-μA
fIN= 32 kHz, fOUT= 96 MHz-900-
JpPeriod jitterfIN= 32 kHz, fOUT= 48 MHz-2.13.2%
fIN= 32 kHz, fOUT= 96 MHz-3.89.2
fIN= 2 MHz, fOUT= 48 MHz-2.23.4
fIN= 2 MHz, fOUT= 96 MHz-5.010.5
tLOCKLock TimeAfter start-up, time to get lock signal.

fIN= 32 kHz, fOUT= 96 MHz

-1.22ms
fIN= 2 MHz, fOUT= 96 MHz-2550μs
DutyDuty cycle405060%
Note:
  1. All values have been characterized with FILTSEL[1/0] as default value.