3.4.6.1 SDMMC1 Connector
A 4-bit full-size SD card connector, J10, connected to the SDMMC1 interface, is mounted on the bottom side of the board. The SDMMC1 communication is based on an 8-pin interface (clock, command, four data and power lines). It includes a card detection and write protect switch.
This connector gives access to the boot environment.
The user can perform a hard reset of the SD card by toggling the PB21 PIO of the MPU, which corresponds to the reset line of the SDMMC1 interface. The same hard reset will be performed automatically at each system reset, when NRST is asserted low.
The hard reset is performed by power cycling the SD card power using the MIC94085YFT high-side load switch. For more details about the MIC94085YFT device, refer to the product web page.
| PIO | Signal Name | Signal Description |
|---|---|---|
|
PB24 |
SDMMC1_DAT0_PB24 |
SDMMC1 data line 0 |
|
PB25 |
SDMMC1_DAT1_PB25 |
SDMMC1 data line 1 |
|
PB26 |
SDMMC1_DAT2_PB26 |
SDMMC1 data line 2 |
|
PB27 |
SDMMC1_DAT3_PB27 |
SDMMC1 data line 3 |
|
PB23 |
SDMMC1_CK_PB23 |
SDMMC1 Clock signal |
|
PB22 |
SDMMC1_CMD_PB22 |
SDMMC1 command line |
|
PB29 |
SDMMC1_CD_PB29 |
SDMMC1 Card Detect signal |
|
PB28 |
SDMMC1_WP_PB28 |
SDMMC1 write-protect line |
|
PB21 |
SDMMC1_NRST_PB21 |
Device reset line |
The SDMMC1 interface supports switching the I/O voltage level from 3.3 V to 1.8 V to enable ultra-high speed modes (such as DDR50 and SDR104) for the SD card. The SAMA7D6 Series MPU will perform the switch by asserting the PB30 PIO on high when a card supporting high-speed modes is detected (depending on software support). The schematic below describes the circuit which generates the required 3.3/1.8V voltages using the adjustable LDO MIC5219.
For more details about the MIC5219 device, refer to the product web page.