16.11.1 CoreSight Identification
A system-level Arm CoreSight ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the Arm Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
| Field | Size | Description | Location |
|---|---|---|---|
| JEP-106 CC code | 4 | Microchip Continuation code: 0x0 | PID4 |
| JEP-106 ID code | 7 | Device ID: 0x29 | PID1+PID2 |
| 4KB count | 4 | Indicates that the CoreSight component is a ROM: 0x0 | PID4 |
| Rev And | 4 | Not used; read as 0 |
PID3 |
| CUSMOD | 4 | Not used; read as 0 |
PID3 |
| PARTNUM | 12 | Contains 0xCD0 to indicate that DSU is present. this indicates that device identification can be completed by reading the Device Identification register (DID). | PID0+PID1 |
| REVISION | 4 | DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. | PID2 |
For additional information, refer to the “Arm Debug Interface Version 5 Architecture Specification”.