36.12.2 USB PHY00 Control Register

Table 36-88. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PHY00
Offset:	0x1500
Reset:	0x0000000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	RXPHSSEL[2:0]			SLEWRATE[1:0]		PREEMP[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:5 – RXPHSSEL[2:0] RX Clock Phase Select

Manually set the Rx Clock phase select. these bits will tune the HS RX path sample timing between digital and analog inside PHY. The delay associated with each step is 256ps.

0x0 = represents the earliest phase

0x07 = represents the latest phase

Bits 4:3 – SLEWRATE[1:0] Adjust FS/LS Slew Rate

These bits will increase/decrease the FS/LS rising/falling time. This tuning can be done when long cable or large capacitance is introduced on DP/DM. It is not applicable for HS signal quality.

0x0: highest slew rate

0x1: middle slew rate

0x2: middle slew rate

0x3 : smallest slew rate