34.6.5.4 Baud
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | BAUD |
| Offset: | 0x0C |
| Reset: | 0x0000 |
| Property: | Enable-Protected, PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BAUD[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BAUD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – BAUD[15:0] Baud Value
Arithmetic Baud Rate Generation
(CTRLA.SAMPR[0]=0):
These bits control the clock generation, as described in the SERCOM Baud Rate section.
If Fractional Baud Rate Generation
(CTRLA.SAMPR[0]=1 or =3) bit positions 15 to 13 are
replaced by FP[2:0] Fractional Part:
-
Bits 15:13 - FP[2:0]: Fractional Part
These bits control the clock generation, as described in the 34.5.2.3 Clock Generation – Baud-Rate Generator section.
-
Bits 12:0 - BAUD[12:0]: Baud Value
These bits control the clock generation, as described in the 34.5.2.3 Clock Generation – Baud-Rate Generator section.