34.6.5.11 Receive Error Count
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | RXERRCNT |
Offset: | 0x20 |
Reset: | 0x00 |
Property: | Read-Synchronized |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RXERRCNT[7:0] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 7:0 – RXERRCNT[7:0] Receive Error Count
This register records the total number of parity errors and NACK errors in ISO7816 mode (CTRLA.FORM=0x7).
This register is automatically cleared on read.