22.6.2 Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG |
| Offset: | 0x01 |
| Reset: | x initially determined from USER CFG page after reset |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WINDOW[3:0] | PER[3:0] | ||||||||
| Access | R/W/CFG | R/W/CFG | R/W/CFG | R/W/CFG | R/W/CFG | R/W/CFG | R/W/CFG | R/W/CFG | |
| Reset | x | x | x | x | x | x | x | x | |
Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period
In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1024 Hz CLK_WDT_OSC clock. These bits are loaded from User Configuration FUCFG0 at start-up.
| Value | Description |
|---|---|
| 0x0 | 8 1kHz clock cycles |
| 0x1 | 16 1kHz clock cycles |
| 0x2 | 32 1kHz clock cycles |
| 0x3 | 64 1kHz clock cycles |
| 0x4 | 128 1kHz clock cycles |
| 0x5 | 256 1kHz clock cycles |
| 0x6 | 512 1kHz clock cycles |
| 0x7 | 1024 1kHz clock cycles |
| 0x8 | 2048 1kHz clock cycles |
| 0x9 | 4096 1kHz clock cycles |
| 0xA | 8192 1kHz clock cycles |
| 0xB | 16384 1kHz clock cycles |
| 0xC-0xF | Reserved |
Bits 3:0 – PER[3:0] Time-Out Period
These bits determine the watchdog time-out period as a number of 1024 Hz CLK_WDTOSC clock cycles. In Window mode operation, these bits define the open window period. These bits are loaded from User Configuration FUCFG0 at startup.
| Value | Description |
|---|---|
| 0x0 | 8 1kHz clock cycles |
| 0x1 | 16 1kHz clock cycles |
| 0x2 | 32 1kHz clock cycles |
| 0x3 | 64 1kHz clock cycles |
| 0x4 | 128 1kHz clock cycles |
| 0x5 | 256 1kHz clock cycles |
| 0x6 | 512 1kHz clock cycles |
| 0x7 | 1024 1kHz clock cycles |
| 0x8 | 2048 1kHz clock cycles |
| 0x9 | 4096 1kHz clock cycles |
| 0xA | 8192 1kHz clock cycles |
| 0xB | 16384 1kHz clock cycles |
| 0xC - 0xF | Reserved |