22.6.3 Early Warning Control

Table 22-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	EWCTRL
Offset:	0x02
Reset:	x initially determined from USER CFG page after reset
Property:	PAC Write-Protection, Enable-Protected


Bit	7	6	5	4	3	2	1	0
					EWOFFSET[3:0]
Access					R/W/CFG	R/W/CFG	R/W/CFG	R/W/CFG
Reset					x	x	x	x

Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset

These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and the generation of the Early Warning interrupt. These bits are loaded from User Configuration FUCFG0 at start-up.

Value	Description
0x0	8 GCLK_WDT clock cycles
0x1	16 GCLK_WDT clock cycles
0x2	32 GCLK_WDT clock cycles
0x3	64 GCLK_WDT clock cycles
0x4	128 GCLK_WDT clock cycles
0x5	256 GCLK_WDT clock cycles
0x6	512 GCLK_WDT clock cycles
0x7	1024 GCLK_WDT clock cycles
0x8	2048 GCLK_WDT clock cycles
0x9	4096 GCLK_WDT clock cycles
0xA	8192 GCLK_WDT clock cycles
0xB	16384 GCLK_WDT clock cycles
0xC - 0xF	Reserved

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