27.5.4.6 Regulators, RAMs, and NVM State in Sleep Modes

Idle sleep mode:

GCLK clocks, regulators, NVM, and RAM are not affected in Idle sleep mode and operate normally.

Standby sleep mode:

By default, in Standby sleep mode, the RAMs, NVM, and regulators are automatically set in Low-Power mode in order to reduce power consumption.

The RAM can be disabled when STDBYCFG.RAMCFG = 0 when the device is in Standby mode. RAM contents are retained.
If not powered-down, the RAM can be set in Low-Power mode according to STDBYCFG.LPRAM.
If neither powered-down nor Low-Power mode is enabled, the RAM data is retained and not set in retention mode. In this case, the wakeup-time is better as there is no need to turn OFF/ON the RAM power-switches.

Hibernate sleep mode:

RAM can be disabled in Hibernate mode and data retained.

If not powered-down, the RAM can be set in low-power mode according to the HIBCFG.LPRAM bit. If in low- power mode, RAM data is retained.

If neither powered-down nor low-power mode, RAM data is retained and not set in retention mode. In this case, the wakeup-time is better as there is no need to turn OFF/ON the RAM power-switches.

In Hibernate mode NVM is powered down.

Backup sleep mode:

The RAMs located in VDDCORE_RAM_PD are powered down.

NVM is powered down.

VDDCORE_RAM_PD is OFF as well as VDDCORE_SW_PD.