46.7.1 PCC Mode Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

Table 46-1. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	MR
Offset:	0x00
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	CID[1:0]
Access	R/W	R/W
Reset	0	0


Bit	23	22	21	20	19	18	17	16
						ISIZE[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8
					FRSTS	HALFS	ALWYS	SCALE
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
			DSIZE[1:0]					PCEN
Access			R/W	R/W				R/W
Reset			0	0				0

Bits 31:30 – CID[1:0] Clear If Disabled

Clears status flags if disabled. These bits are useful to re-initialize the internal mechanism of the PCC to avoid corrupted data due to glitches. Each time a falling edge of the selected DEN1 or DEN2 signal is detected, the internal mechanism of the PCC is re-initialized to avoid alignment issues.

Value	Description
0x0	Clear not enabled
0x1	Clear on falling edge on DEN1 enabled
0x2	Clear on falling edge on DEN2 enabled
0x3	Clear on falling edge on either DEN1 or DEN2 enabled

Bits 18:16 – ISIZE[2:0] Input Data Size

Value	Name	Description
0x0	8BITS	Input data bus size is 8 bits
0x1	10BITS	Input data bus size is 10 bits
0x2	12BITS	Input data bus size is 12 bits
0x3	14BITS	Input data bus size is 14 bits

Bit 11 – FRSTS First Sample

This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an index from 0 to n.

Value	Description
0	Only data with an even index are sampled.
1	Only data with an odd index are sampled.

Bit 10 – HALFS Half Sampling

This function is independent from the ALWYS bit.

Value	Description
0	The Parallel Capture Controller samples all the data.
1	The Parallel Capture Controller samples the data only every other time.

Bit 9 – ALWYS Always Sampling

Value	Description
0	The parallel capture Controller samples the data when both data enables are active.
1	The parallel capture controller always samples the data, regardless of the state of data enable.

Bit 8 – SCALE Scale Data

Value	Description
0	No effect.
1	When input data size is not equal to 8 bits (ISIZE ≠ 0), the data stored in the PCC_RHR is automatically up-scaled to 16 bits.

Bits 5:4 – DSIZE[1:0] Data Size

Value	Name	Description
0x0	1DATA	1 data is read in the PCC_RHR
0x1	2DATA	2 data are read in the PCC_RHR
0x2	4DATA	4 data are read in the PCC_RHR (only for 8 bits data size, ISIZE = 0)
0x3	-	Reserved

Bit 0 – PCEN Parallel Capture Enable

Value	Description
0	The Parallel Capture Controller is disabled.
1	The Parallel Capture Controller is enabled.