46.7.5 Interrupt Status Register

Table 46-5. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: ISR
Offset: 0x10
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       OVREDRDY 
Access RR 
Reset 00 

Bit 1 – OVRE Overrun Error Interrupt Status

The OVRE flag is automatically reset when this register is read or when the PCC is disabled.
ValueDescription
0 No overrun error occurred since the last read of this register.
1 At least one overrun error occurred since the last read of this register.

Bit 0 – DRDY Data Ready Interrupt Status

The DRDY flag is automatically reset when RHR is read or when the PCC is disabled.
ValueDescription
0 No new data is ready to be read since the last read of RHR.
1 New data is ready to be read since the last read of RHR.