46.5.2 Clocks

The PCC bus clock (CLK_APB_PCC) is provided by the 20 Main Clock (MCLK) through the AHB-APB C bridge. The clock is enabled and disabled by writing the MSK12 bit the in the MCLK.CLKMSK3 register (MCLK.CLKMSK3[12]).

For capturing operation, the external device has to provide a PCC clock signal (PCC_CLK) synchronous to the data received (pixel clock) through a pin. Refer to the PORT and the Pinout table for additional information.

Writing any of the registers does not require the PCC_CLK to be enabled.