24.7.15 Tamper ID

Important: The DMA reads the TAMPID register with an outdated value when triggered through the EVSYS. A secondary read of the TAMPID register is required to get accurate data.

Table 24-18. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	TAMPID
Offset:	0x68
Reset:	0x00000000


Bit	31	30	29	28	27	26	25	24
	TAMPEVT
Access	R/W
Reset	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	TAMPID7	TAMPID6	TAMPID5	TAMPID4	TAMPID3	TAMPID2	TAMPID1	TAMPID0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – TAMPEVT Tamper Event Detected

Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit.

Value	Description
0	A tamper input event has not been detected
1	A tamper input event has been detected

Bits 0, 1, 2, 3, 4, 5, 6, 7 – TAMPIDn Tamper on Channel n Detected [n=0..7]

Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit.

Value	Description
0	A tamper condition has not been detected on Channel n
1	A tamper condition has been detected on Channel n