24.7 Register Summary - 32-bit Counter Mode

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.

OffsetNameBit Pos.76543210
0x00CTRLA7:0MATCHCLR   MODE[1:0]ENABLESWRST
15:8COUNTSYNCGPTRST  PRESCALER[3:0]
0x02CTRLB7:0DMAENRTCOUTDEBASYNCDEBMAJ  GP2ENGP0EN
15:8SEPTOACTF[2:0] DEBF[2:0]
0x04EVCTRL7:0PEREO7PEREO6PEREO5PEREO4PEREO3PEREO2PEREO1PEREO0
15:8OVFEOTAMPEREO    CMPEO0[1:0]
23:16       TAMPEVEI
31:24       PERDEO
0x08INTENCLR7:0PER7PER6PER5PER4PER3PER2PER1PER0
15:8OVFTAMPER    CMP1CMP0
0x0AINTENSET7:0PER7PER6PER5PER4PER3PER2PER1PER0
15:8OVFTAMPER    CMP1CMP0
0x0CINTFLAG7:0PER7PER6PER5PER4PER3PER2PER1PER0
15:8OVFTAMPER    CMP1CMP0
0x0EDBGCTRL7:0       DBGRUN

0x0F

Reserved         
0x10SYNCBUSY7:0 COMP1COMP0 COUNTFREQCORRENABLESWRST
15:8COUNTSYNC       
23:16    GP3GP2GP1GP0
31:24        
0x14FREQCORR7:0SIGNVALUE[6:0]

0x15

...

0x17

Reserved         
0x18COUNT7:0COUNT[7:0]
15:8COUNT[15:8]
23:16COUNT[23:16]
31:24COUNT[31:24]

0x1C

...

0x1F

Reserved         
0x20COMP07:0COMP[7:0]
15:8COMP[15:8]
23:16COMP[23:16]
31:24COMP[31:24]
0x24COMP17:0COMP[7:0]
15:8COMP[15:8]
23:16COMP[23:16]
31:24COMP[31:24]

0x28

...

0x3F

Reserved         
0x40GP07:0GP[7:0]
15:8GP[15:8]
23:16GP[23:16]
31:24GP[31:24]
0x44GP17:0GP[7:0]
15:8GP[15:8]
23:16GP[23:16]
31:24GP[31:24]
0x48GP27:0GP[7:0]
15:8GP[15:8]
23:16GP[23:16]
31:24GP[31:24]
0x4CGP37:0GP[7:0]
15:8GP[15:8]
23:16GP[23:16]
31:24GP[31:24]

0x50

...

0x5F

Reserved         
0x60TAMPCTRL7:0IN3ACT[1:0]IN2ACT[1:0]IN1ACT[1:0]IN0ACT[1:0]
15:8IN7ACT[1:0]IN6ACT[1:0]IN5ACT[1:0]IN4ACT[1:0]
23:16TAMLVL7TAMLVL6TAMLVL5TAMLVL4TAMLVL3TAMLVL2TAMLVL1TAMLVL0
31:24DEBNC7DEBNC6DEBNC5DEBNC4DEBNC3DEBNC2DEBNC1DEBNC0
0x64TIMESTAMP7:0COUNT[7:0]
15:8COUNT[15:8]
23:16COUNT[23:16]
31:24COUNT[31:24]
0x68TAMPID7:0TAMPID7TAMPID6TAMPID5TAMPID4TAMPID3TAMPID2TAMPID1TAMPID0
15:8        
23:16        
31:24TAMPEVT       
0x6CTAMPCTRLB7:0ALSI7ALSI6ALSI5ALSI4ALSI3ALSI2ALSI1ALSI0
15:8        
23:16        
31:24