31.4 Signal Interface
The ETH Controller module includes the following signal interfaces:
- MII and RMII to an external PHY
- MDIO interface for external PHY management
- Client APB interface for accessing ETH registers
- Host AXI interface for memory access
- TSUCOMP signal for TSU timer count value comparison
| Signal Name | Function | MII | RMII |
|---|---|---|---|
| ETH_TXCK1(1) | Transmit Clock or Reference Clock | TXCK | REFCK |
| ETH_TXEN | Transmit Enable | TXEN | TXEN |
| ETH_TX[7:0] | Transmit Data | TXD[3:0] | TXD[1:0] |
| ETH_TXER | Transmit Coding Error | TXER | Not Used |
| ETH_RXCK | Receive Clock | RXCK | Not Used |
| ETH_RXDV | Receive Data Valid | RXDV | CRSDV |
| ETH_RX[7:0] | Receive Data | RXD[3:0] | RXD[1:0] |
| ETH_RXER | Receive Error | RXER | RXER |
| ETH_CRS | Carrier Sense and Data Valid | CRS | Not Used |
| ETH_COL | Collision Detect | COL | Not Used |
| ETH_MDC | Management Data Clock | MDC | MDC |
| ETH_MDIO | Management Data Input/Output | MDIO | MDIO |
Note:
- Input only. ETH_TXCK1 must be provided with a 25 MHz / 50 MHz clock for MII / RMII interfaces, respectively.