33.12.12 Event Input Control

There are up to four input event pins for each PORT group. Each byte of this register addresses one Event input pin.

Table 33-15. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit
Name: EVCTRL
Offset: 0x2C
Reset: 0x00000000
Property: PAC Write-Protection, Secure

Bit 3130292827262524 
 PORTEI3EVACT3[1:0]PID3[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 PORTEI2EVACT2[1:0]PID2[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 PORTEI1EVACT1[1:0]PID1[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 PORTEI0EVACT0[1:0]PID0[4:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7, 15, 23, 31 – PORTEIx PORT Event Input Enable x [x = 3..0]

ValueDescription
0 The event action x (EVACTx) will not be triggered on any incoming event.
1 The event action x (EVACTx) will be triggered on any incoming event.

Bits 5:6, 13:14, 21:22, 29:30 – EVACTx PORT Event Action x [x = 3..0]

These bits define the event action the PORT will perform on event input x.

Bits 0:4, 8:12, 16:20, 24:28 – PIDx PORT Event Pin Identifier x [x = 3..0]

These bits define the I/O pin on which the event action will be performed, according to the following table.

Table 33-16. PORT Event x Action ( x = [3..0] )
Value Name Description
0x0 OUT Output register of pin will be set to level of event.
0x1 SET Set output register of pin on event.
0x2 CLR Clear output register of pin on event.
0x3 TGL Toggle output register of pin on event.
Table 33-17. PORT Event x Pin Identifier ( x = [3..0] )
Value Name Description
0x0 PIN0 Event action to be executed on PIN 0.
0x1 PIN1 Event action to be executed on PIN 1.
... ... ...
0x31 PIN31 Event action to be executed on PIN 31.