33.12.11 Write Configuration

This Write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral multiplexing.

In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero.

Table 33-14. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: WRCONFIG
Offset: 0x28
Reset: 0x00000000
Property: PAC Write-Protection, Write-Only

Bit 3130292827262524 
 HWSELWRPINCFG WRPMUXPMUX[3:0] 
Access WWWWWWW 
Reset 0000000 
Bit 2322212019181716 
   SLEWLIM[1:0]ODRAINPULLENINENPMUXEN 
Access WWWWWW 
Reset 000000 
Bit 15141312111098 
 PINMASK[15:8] 
Access WWWWWWWW 
Reset 00000000 
Bit 76543210 
 PINMASK[7:0] 
Access WWWWWWWW 
Reset 00000000 

Bit 31 – HWSEL Half-Word Select

This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation.

This bit will always read as zero.

ValueDescription
0 The lower 16 pins of the PORT group will be configured.
1 The upper 16 pins of the PORT group will be configured.

Bit 30 – WRPINCFG Write PINCFG

This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.

Writing '0' to this bit has no effect.

Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.SLEWLIM, WRCONFIG.ODRAIN, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.

This bit will always read as zero.

ValueDescription
0 The PINCFGn registers of the selected pins will not be updated.
1 The PINCFGn registers of the selected pins will be updated.

Bit 28 – WRPMUX Write PMUX

This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXm, m=0,...15) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.

Writing '0' to this bit has no effect.

Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG. PMUX value.

This bit will always read as zero.

Note: Not all PINCFGn registers are supported by all I/O port groups.
ValueDescription
0 The PMUXm registers of the selected pins will not be updated.
1 The PMUXm registers of the selected pins will be updated.

Bits 27:24 – PMUX[3:0] Peripheral Multiplexing

These bits determine the new value written to the Peripheral Multiplexing register (PMUXm, m = 0,...15) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.

These bits will always read as zero.

Bits 21:20 – SLEWLIM[1:0] Output Driver Slew Rate Selection

This bit determines the new value written to PINCFGn.SLEWLIM for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

Note:
  1. Only some pins have output TRISE/TFALL slew limit control.
  2. Slew rate control can be used to improve signal integrity for high-speed signals if improper external HDW resistor termination was not utilized. One side effect however can be that if excessive slew is used it can affect maximum signal rates.
  3. If an I2C function is enabled on a pin, set PINCFGn.SLEWLIM = 0x00 (disabled).
ValueDescription
0x00 Slew rate control disabled (fast rise/fall time operation)
0x01 Slew rate control enabled (4x slower)
0x02 Slew rate control enabled (8x slower)
0x03 Slew rate control enabled (12x slower)

Bit 19 – ODRAIN Open Drain Output

This bit determines the new value written to PINCFGn.ODRAIN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

ValueDescription
0 Output pin is Totem Pole (i.e. Push-Pull) output
1 Open drain output is enabled

Bit 18 – PULLEN Pull Enable

This bit determines the new value written to PINCFGn.PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

ValueDescription
0 Internal pin Pull-Up is disabled
1 Internal pin Pull-Up is enabled

Bit 17 – INEN Input Enable

This bit determines the new value written to PINCFGn.INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

ValueDescription
0 Disable input pin function
1 Enable input pin function

Bit 16 – PMUXEN Peripheral Multiplexer Enable

This bit determines the new value written to PINCFGn.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

ValueDescription
0 The peripheral multiplexer selection is disabled, and the PORT registers control the direction and output drive value.
1 The peripheral multiplexer selection is enabled and the selected peripheral function controls the direction and output drive value.

Bits 15:0 – PINMASK[15:0] Pin Mask for Multiple Pin Configuration

These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.

These bits will always read as zero.

ValueDescription
0 The configuration of the corresponding I/O pin in the half-word group will be left unchanged.
1 The configuration of the corresponding I/O pin in the half-word PORT group will be updated.