25.1 Overview

The Direct Memory Access (DMA) Controller implements data transfers across the system bus without the intervention of the CPU, normally in a stream fashion called a burst of (32-bit) word transfers (beats).

The DMA Controller module 0 has 8 channels, and DMA Controller module 1 has 4 channels. Please see the Block Diagram for a DMA Controller top-level block diagram.

The DMA Controller data path comprises:

  • A DMA Read Bus Host (DMAR ), common to all DMA Channels
  • A DMA Write Bus Host (DMAW), common to all DMA Channels
  • Small data FIFOs to handle the data in transit from the Source to Destination, with one FIFO per each DMA Channel (FIFO0 to FIFON-11 in the Block Diagram)

The DMA Controller is useful in one of the four configurations presented in the following figures.

Figure 25-1. Input Configuration
Figure 25-2. Output Configuration
Figure 25-3. Input/Output Configuration
Figure 25-4. Transfer Configuration