25.4 Peripheral Dependencies
| Peripheral
Name |
Base Address | NVIC IRQ Index: Source | MCLK AHBx/APBx Clock Enable Mask Bit |
PAC Peripheral
Identifier (PAC.WRCTRL.PERIDx) |
EVSYS Users
(EVSYS.USERm) |
EVSYS Generator
(EVSYS.CHANNELn.EVGENx) |
Power Domain |
|---|---|---|---|---|---|---|---|
| DMA0 | 0x4480_2000 | 33 : Priority 0 34 : Priority 1 35 : Priority 2 |
AHB : MCLK.CLKMSK0[8] APB : MCLK.CLKMSK2[1] |
21 | 6-13 : CHx_Start, x=0,1,…7 14-21 : CHx_Aux, x=0,1…7 |
38-45 : DMA0_CHx, x=0,1,…7 | VDDCORE_SW |
| DMA1 | 0x4480_4000 | 36 : Priority 0 37 : Priority 1 |
AHB : MCLK.CLKMSK0[9] APB : MCLK.CLKMSK2[2] |
22 | 22-25 : CHx_Start, x=0,1,2,3 26-29 : CHx_Aux, x=0,1,2,3 |
46-49 : DMA1_CHx, x=0,1,2,3 | VDDCORE_SW |
Power Management
The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC’s interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. On hardware or software reset, all registers are set to their reset value.
Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue operation during debugging. Refer to DBGCTRL SFR for details.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except the following registers:
- Interrupt Priority Status Registers (INTSTATn)
- Channel Interrupt Registers (CHINTENCLRn, CHINTENSETn, CHINTFn)
- All of the channel status registers
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger.