21.7.5 Clock Selection Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CLKSELCTRL |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HSMSEL[1:0] | RTCSEL[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 5:4 – HSMSEL[1:0] HASM - Hardware Security Module, (HSM), Clock Select
These bits select the HSM clock source.
| Value | Name | Description |
|---|---|---|
0x0 |
ULP32K | Clock from 32 kHz internal ULP oscillator |
0x1 |
- | Reserved, (defaults to ULP32K) |
0x2 |
XOSC32K | 32.768 kHz from 32 kHz external crystal oscillator |
0x3 |
- | Reserved, (defaults to ULP32K) |
Note: If a reserved value is written, the ULP32K internal ULP oscillator is selected as
source for the HSM clock by default.
Bits 1:0 – RTCSEL[1:0] RTC Clock Selection
These bits select the RTC clock source.
| Value | Name | Description |
|---|---|---|
0x0 |
ULP32K | 32 kHz from 32 kHz internal ULP oscillator |
0x1 |
ULP1K | 1 kHz from 32 kHz internal ULP oscillator |
0x2 |
XOSC32K | 32.768 kHz from 32 kHz external crystal oscillator |
0x3 |
XOSC1K | 1.024 kHz from 32 kHz external oscillator |