21.7.4 Status

Table 21-5. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: STATUS
Offset: 0x0C
Reset: 0x00000000
Property: –

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     XOSC32KSWXOSC32KFAIL XOSC32KRDY 
Access R/HS/HCR/HS/HCR/HS/HC 
Reset 000 

Bit 3 – XOSC32KSW XOSC32K 32.768kHz Clock Switch

Note: This bit is set by hardware if a 32.768kHz clock fail detect occurs and clock fail detect is enabled, (i.e. CFDCTRL.CFDEN =1 and INTFLAG.XOSC32KFAIL=1 or STATUS.XOSC32KFAIL=1).
ValueDescription
0 XOSC32K is not switched and the clock source is provided by the external 32.768kHz oscillator source.
1 XOSC32K is switched to the internal OSCULP32K oscillator clock. Both 32.768kHz and 1.024kHz outputs of the XOSC32K are replaced by the respective OSCULP32K 32 kHz and 1 kHz outputs to the respective logic modules.

Bit 2 – XOSC32KFAIL XOSC32K 32.768kHz Clock Failure Detect

Note: This bit is set by hardware if a 32.768kHz clock fail detect occurs and clock fail detect is enabled, (i.e. CFDCTRL.CFDEN =1 and INTFLAG.XOSC32KFAIL=1).
ValueDescription
0 No XOSC32K 32.768kHz clock fail detection.
1 XOSC32K 32.768kHz external crystal/clock fail detect. Hardware clock switch will be initiated to OSCULP32K oscillator clocks.

Bit 0 – XOSC32KRDY XOSC32K Ready

Note: This bit is set and cleared by hardware based on the status of the of the active XOSC32K 32.768kHz clock source.
ValueDescription
0 XOSC32K is not ready.
1 XOSC32K is stable and ready to be used as a clock source.