21.7.1 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET).
Table 21-2. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: INTENCLR
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      XOSC32KFAIL XOSC32KRDY 
Access R/W/HCR/W/HC 
Reset 00 

Bit 2 – XOSC32KFAIL XOSC32K 32.768kHz Clock Failure Detect Interrupt Enable

Note: Writing a '0' to this bit has no effect.

This bit is cleared under the following conditions:

  • Writing a '1' to this bit will clear the XOSC32K Clock Fail Interrupt Enable bit, (i.e. XOSC32KFAIL), which disables the XOSC32K Clock Failure interrupt
  • Writing a one to the same corresponding bit in the INTENSET register
ValueDescription
0 The XOSC32K Clock Fail Detect Interrupt is disabled.
1 The XOSC32K Clock Fail Detect Interrupt is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set.

Bit 0 – XOSC32KRDY XOSC32K 32.768kHz Ready Interrupt Enable

Note: Writing a '0' to this bit has no effect.

This bit is cleared under the following conditions:

  • Writing a '1' to this bit, (XOSC32KRDY), will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt
  • Writing a one to the same corresponding bit in the INTENSET register
ValueDescription
0 The XOSC32K Ready interrupt is disabled.
1 The XOSC32K Ready interrupt is enabled.