32.8.8 Channel n Control

This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.

Table 32-9. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CHANNELn
Offset:	0x20 + n*0x08 [n=0..7]
Reset:	0x00008000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	ONDEMAND	RUNSTDBY			EDGSEL[1:0]		PATH[1:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	1	0			0	0	0	0


Bit	7	6	5	4	3	2	1	0
	EVGEN[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 15 – ONDEMAND Generic Clock On Demand

Value	Description
0	Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled.
1	Generic clock is requested on demand while an event is handled

Bit 14 – RUNSTDBY Run in Standby

This bit is used to define the behavior during standby sleep mode.

Value	Description
0	The channel is disabled in standby sleep mode.
1	The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND bit.

Bits 11:10 – EDGSEL[1:0] Edge Detection Selection

These bits set the type of edge detection to be used on the channel.

These bits must be written to zero when using the asynchronous path.

Value	Name	Description
0x0	NO_EVT_OUTPUT	No event output when using the resynchronized or synchronous path
0x1	RISING_EDGE	Event detection only on the rising edge of the signal from the event generator
0x2	FALLING_EDGE	Event detection only on the falling edge of the signal from the event generator
0x3	BOTH_EDGES	Event detection on rising and falling edges of the signal from the event generator

Bits 9:8 – PATH[1:0] Path Selection

These bits are used to choose which path will be used by the selected channel.

Note: The path choice can be limited by the channel source. Only a channel with an index less than12, embeds synchronous/resynchronous capabilities. The rest of available channels support only asynchronous path selection.

Important: When synchronous or resynchronized path is enabled, event inversion feature in peripherals must not be enabled (EVCTRL.xxxINV = 0.

Important: To avoid spurious EVSYS detections, EVSYS must be write protected by configuring the WRCTRL register in the PAC before being used.

Value	Name	Description
0x0	SYNCHRONOUS	Synchronous path
0x1	RESYNCHRONIZED	Resynchronized path
0x2	ASYNCHRONOUS	Asynchronous path
Other	-	Reserved

Bits 7:0 – EVGEN[7:0] Event Generator Selection

These bits are used to choose the event generator to connect to the selected channel.

Table 32-10. Event Generator (EVGEN) Mapping
Module Name	Name of Generator	Value	Description
SUPC	SUPC LVDET	1	Low Voltage Detection
OSCCTRL	XOSC FAIL	2	XOSC fail detection
OSC32KCTRL	XOSC32K_FAIL	3	XOSC32K fail detection
FREQM	DONE	4	Measurement Done
FREQM	WINMON	5	Window Monitor Condition Met
RTC	RTC-PERx	6-13	RTC period x=0..7
	PERD	14	RTC Daily Period
	RTC-CMPx	15-18	RTC comparison x=0..3
	RTC-TAMPER	19	RTC tamper detection
	RTC-OVF	20	RTC overflow
EIC	EXTINTx	21-36	EIC external interrupt x=0..15
PAC	PAC_ACCERR	37	PAC Access Error
DMA0	DMA0_CHx	38-45	DMA channel x=0…7
DMA1	DMA1_CHx	46-49	DMA channel x=0…3
TCC0	OVF	50	TCC0 Overflow
	TRG	51	TCC0 Trigger Event
	CNT	52	TCC0 Counter
	MCx	53-58	TCC0 Match/Compare x=0..5
TCC1	OVF	59	TCC1 Overflow
	TRG	60	TCC1 Trigger Event
	CNT	61	TCC1 Counter
	MCx	62-67	TCC1 Match/Compare x=0..5
TCC2	OVF	68	TCC2 Overflow
	TRG	69	TCC2 Trigger Event
	CNT	70	TCC2 Counter
	MCx	71-76	TCC2 Match/Compare x=0..5
TCC3	OVF	77	TCC3 Overflow
	TRG	78	TCC3 Trigger Event
	CNT	79	TCC3 Counter
	MCx	80-85	TCC3 Match/Compare x=0..5
TCC4	OVF	86	TCC4 Overflow
	TRG	87	TCC4 Trigger Event
	CNT	88	TCC4 Counter
	MCx	89,90	TCC4 Match/Compare x=0..1
TCC5	OVF	91	TCC5 Overflow
	TRG	92	TCC5 Trigger Event
	CNT	93	TCC5 Counter
	MCx	94,95	TCC5 Match/Compare x=0..1
TCC6	OVF	96	TCC6 Overflow
	TRG	97	TCC6 Trigger Event
	CNT	98	TCC6 Counter
	MCx	99,100	TCC6 Match/Compare x=0..1
TCC7	OVF	101	TCC7 Overflow
	TRG	102	TCC7 Trigger Event
	CNT	103	TCC7 Counter
	MCx	104,105	TCC7 Match/Compare x=0..1
ADC	ADC RESRDY	106	ADC Ready
ADC	ADC CMP	107	ADC Compare Event
AC	AC COMPx	108,109	AC Comparator x=0..1
AC	AC WIN	110	AC0 Window
PTC	EOC	111	PTC end of Conversion
PTC	WCOMP	112	PTC Window Compare
SPI_IXS	GEN	113	Frame Pulse (??)
CCL	LUTOUT_x	114-117	LUTx Output, x=0…3
PDEC	DIR	118	Direction Output
	ERR	119	Error Output
	MCX_0	121	Match Channel 0
	MCX_1	122	Match Channel 1
	VLC	123	Velocity Output
ETH	TSU_CMP	124	Time Stamp Unit (TSU) Compare
TRNG	READY	125	TRNG ready

Note:

A = Asynchronous path, S = Synchronous path, R = Resynchronized path