39.8.2 SMC Pulse Register
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | PULSE |
Offset: | 0x04 + n*0x04 [n=0..3] |
Reset: | 0x01010101 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
NCS RD PULSE[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
NRD PULSE[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NCS WR PULSE[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NWE PULSE[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 30:24 – NCS RD PULSE[6:0] NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS RD PULSE[6] + NCS RD PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle.
In Page mode read access, the NCS RD PULSE parameter defines the duration of the first access to one page.
Bits 22:16 – NRD PULSE[6:0] NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD pulse length = (256* NRD PULSE[6] + NRD PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In Page mode read access, the NRD PULSE parameter defines the duration of the subsequent accesses in the page.
Bits 14:8 – NCS WR PULSE[6:0] NCS Pulse Length in WRITE Address
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS WR PULSE[6] + NCS WR PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle.
Bits 6:0 – NWE PULSE[6:0] NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256* NWE PULSE[6] + NWE PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.