18.6.6 OSCCTRL Interrupts

The OSCCTRL has the following interrupt sources:

• XOSCRDY - Multipurpose Crystal Oscillator Ready: A “0-to-1” transition on the STATUS.XOSCRDY bit is detected
• XOSCFAIL - Xosc Startup Failure: A “0-to-1” transition on the STATUS.XOSCFAIL bit is detected
• CLKFAIL - Xosc Clock Failure: A “0-to-1” transition on the STATUS.CLKFAIL bit is detected
• DFLLRDY - DFLL48m Ready: A “0-to-1” transition on the STATUS.DFLLRDY bit is detected
• DFLLLOCK - DFLL48m Lock: A “0-to-1” transition on the STATUS.DFLLLOCK bit is detected
• DFLLOVF - DFLL48m Overflow: A “0-to-1” transition on the STATUS.DFLLOVF bit is detected
• DFLLUNF - DFLL48m Underflow: A “0-to-1” transition on the STATUS.DFLLUNF bit is detected
• DFLLRCS - DFLL48m Reference Clock Stop: A “0-to-1” transition on the STATUS.DFLLRCS bit is detected
• DFLLFAIL - DFLL Startup Failure: A “0-to-1” transition on the STATUS.DFLLFAIL bit is detected

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set register (INTENSET) and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set, and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the OSCCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags.

The OSCCTRL has fewer request lines than interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present.