18.7.4 Interrupt Flag Status and Clear

Note: Subsequent to an interrupt flag being cleared, the flag must be read back to verify the clear before exiting the ISR. Failure to do this can result in duplicate interrupts.
Table 18-7. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: INTFLAG
Offset: 0x0C
Reset: 0x00000000

Bit 3130292827262524 
        PLL0LOCKR 
Access HS/R/W 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   DFLLFAILDFLLRCSDFLLUNFDFLLOVFDFLLLOCKDFLLRDY 
Access HS/R/WHS/R/WHS/R/WHS/R/WHS/R/WHS/R/W 
Reset 000000 
Bit 76543210 
      CLKFAILXOSCFAILXOSCRDY 
Access HS/R/WHS/R/WHS/R/W 
Reset 000 

Bit 24 – PLL0LOCKR PLL Lock Rise

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the PLL Lock and will generate an interrupt request if INTENSET.PLLLOCKR is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the PLL Lock Rise interrupt flag.

Note: This bit is only valid for the first time it sets, when the PLL locks. This bit should be ignored afterwards, and the interrupt disabled so there are no unexpected interrupts.

Bit 13 – DFLLFAIL DFLL Startup Failure

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the DFLL Startup Failure bit in the Status register (STATUS.DFLLFAIL) and will generate an interrupt request if INTENSET.DFLLFAIL is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the DFLL Startup Failure interrupt flag.

Bit 12 – DFLLRCS DFLL Reference Clock Stopped

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register (STATUS. DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the DFLL Reference Clock Stopped interrupt flag.

Bit 11 – DFLLUNF DFLL Tuner Underflow

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the DFLL Tuner Underflow bit in the Status register (STATUS.DFLLUNF) and will generate an interrupt request if INTENSET.DFLLUNF is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the DFLL Tuner Underflow interrupt flag.

Bit 10 – DFLLOVF DFLL Tuner Overflow

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the DFLL Tuner Overflow bit in the Status register (STATUS.DFLLOVF) and will generate an interrupt request if INTENSET.DFLLOVF is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the DFLL Tuner Overflow interrupt flag.

Bit 9 – DFLLLOCK DFLL Lock

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the DFLL Lock bit in the Status register (STATUS.DFLLLOCK) and will generate an interrupt request if INTENSET.DFLLLOCK is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the DFLL Lock interrupt flag.

Bit 8 – DFLLRDY DFLL Ready

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (STATUS.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the DFLL Ready interrupt flag.

Bit 2 – CLKFAIL XOSC Clock Failure

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the XOSC Clock Failure bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the XOSC Clock Failure interrupt flag.

Bit 1 – XOSCFAIL XOSC Startup Failure

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the XOSC Startup Failure bit in the Status register (STATUS.XOSCFAIL) and will generate an interrupt request if INTENSET.XOSCFAIL is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the XOSC Startup Failure interrupt flag.

Bit 0 – XOSCRDY XOSC Ready

This flag is cleared by writing a '1' to it.

This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'.

Writing a ‘0’ to this bit has no effect.

Writing a '1' to this bit clears the XOSC Ready interrupt flag.