18.7 Register Summary

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	EVCTRL	7:0								CFDEO
		15:8
		23:16
		31:24
0x04	INTENCLR	7:0						CLKFAIL	XOSCFAIL	XOSCRDY
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		23:16
		31:24								PLL0LOCKR
0x08	INTENSET	7:0						CLKFAIL	XOSCFAIL	XOSCRDY
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		23:16
		31:24								PLL0LOCKR
0x0C	INTFLAG	7:0						CLKFAIL	XOSCFAIL	XOSCRDY
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		23:16
		31:24								PLL0LOCKR
0x10	STATUS	7:0					XOSCCKSW	CLKFAIL	XOSCFAIL	XOSCRDY
		15:8			DFLLFAIL	DFLLRCS	DFLLUNF	DFLLOVF	DFLLLOCK	DFLLRDY
		23:16
		31:24
0x14	XOSCCTRLA	7:0	ONDEMAND		SWBEN	CFDEN	XTALEN	AGC	ENABLE
		15:8					STARTUP[3:0]
		23:16					CFDPRESC[3:0]
		31:24	WRTLOCK						USBHSDIV[1:0]
0x18	XOSCCTRLB	7:0				GBW[1:0]		GRES	GMAN[1:0]
		15:8
		23:16
		31:24	WRTLOCK
0x1C ... 0x2B	Reserved
0x2C	DFLLCTRLA	7:0	ONDEMAND				LOWFREQ	WRTLOCK	ENABLE
		15:8
		23:16
		31:24
0x30	DFLLCTRLB	7:0	WAITLOCK		QLDIS	CCDIS		LLAW	STABLE	LOOPEN
		15:8
		23:16
		31:24
0x34	DFLLTUNE	7:0		TUNE[6:0]
		15:8
		23:16
		31:24
0x38	DFLLDIFF	7:0	DIFF[7:0]
		15:8	DIFF[15:8]
		23:16
		31:24
0x3C	DFLLMUL	7:0	MUL[7:0]
		15:8	MUL[15:8]
		23:16		STEP[6:0]
		31:24
0x40	PLL0CTRL	7:0	ONDEMAND					WRTLOCK	ENABLE
		15:8			BWSEL[2:0]			REFSEL[2:0]
		23:16
		31:24
0x44	PLL0FBDIV	7:0	FBDIV[7:0]
		15:8							FBDIV[9:8]
		23:16
		31:24
0x48	PLL0REFDIV	7:0			REFDIV[5:0]
		15:8
		23:16
		31:24
0x4C	PLL0POSTDIVA	7:0	OUTEN0		POSTDIV0[5:0]
		15:8	OUTEN1		POSTDIV1[5:0]
		23:16	OUTEN2		POSTDIV2[5:0]
		31:24	OUTEN3		POSTDIV3[5:0]
0x50	PLL0POSTDIVB	7:0	OUTEN4		POSTDIV4[5:0]
		15:8	OUTEN5		POSTDIV5[5:0]
		23:16
		31:24
0x54 ... 0x6B	Reserved
0x6C	FRACDIV0	7:0	REMDIV[0]
		15:8	REMDIV[8:1]
		23:16	INTDIV[7:0]
		31:24		INTDIV[14:8]
0x70 ... 0x77	Reserved
0x78	SYNCBUSY	7:0		FRACDIV0	DFLLMUL	DFLLDIFF	DFLLTUNE	DFLLCTRLB	DFLLENABLE
		15:8
		23:16
		31:24

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