21.6.6 Peripheral BUS Clock Enable Mask1 Register

Note: AHB = Advanced High-performance Bus

APB = Advanced Peripheral Bus

Table 21-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CLKMSK1
Offset:	0x40
Reset:	0x0006_FFFF
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					MSK19	MSK18
Access					R/W	R/W
Reset					1	0


Bit	15	14	13	12	11	10	9	8
	MSK15	MSK14	MSK13	MSK12	MSK11	MSK10
Access	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	MSK7	MSK6	MSK5			MSK2	MSK1	MSK0
Access	R/W	R/W	R/W			R/W	R/W	R/W
Reset	1	1	1			1	1	1

Bits 18, 19 – MSKn Clock Enable Mask n

Bits 10, 11, 12, 13, 14, 15 – MSKn Clock Enable Mask n

Bits 5, 6, 7 – MSKn Clock Enable Mask n

Bits 0, 1, 2 – MSKn Clock Enable Mask n


Bit Number	Module
0	DSU_APB
1	FCR
2	FCW
5	RSTC
6	OSCCTRL
7	OSC32KCTRL
10	FREQM
11	WDT
12	RTC
13	EIC
14	PAC
15	TRAM
18	MBISTINTF
19	TDM

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