Jump to main content
21.6.5 Peripheral BUS Clock Enable Mask0 Register
Note: AHB = Advanced High-performance
Bus
APB = Advanced Peripheral Bus
Table 21-6. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: CLKMSK0 Offset: 0x3C Reset: 0x007F_FFFF Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 MSK22 MSK21 MSK20 MSK19 MSK18 MSK17 MSK16 Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 MSK15 MSK14 MSK13 MSK12 MSK9 MSK8 Access R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0 MSK6 MSK5 MSK4 MSK3 Access R/W R/W R/W R/W Reset 1 1 1 1
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 – MSKn Clock Enable Mask
Bits 8, 9 – MSKn Clock Enable Mask
Bits 0, 1, 2, 3 – MSKn Clock Enable Mask
Bit Number Module 3 DSU_AHB 4 FCR 5 FCW 6 PAC 8 DMA0 9 DMA1 12 PRM 13 CAN0 14 CAN1 15 ETH 16 SQI 17 SDMMC0 18 SDMMC1 19 USBFS 20 USBHS 21 EBI 22 HSM
On this page
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 – MSKn Clock Enable Mask Bits 8, 9 – MSKn Clock Enable Mask Bits 0, 1, 2, 3 – MSKn Clock Enable Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
