13.7.5 AHB Slave Bus Interrupt Flag Status and Clear
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
| Name: | INTFLAGAHB |
| Offset: | 0x10 |
| Reset: | 0x000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| HSRAMLP | L2HBRIDGES | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LPRAMDMAC | LPRAMPICOP | LPRAMHS | HPB4 | HPB3 | HPB2 | HPB0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| H2LBRIDGES | HPB1 | HSRAMDSU | HSRAMCM0P | FLASH | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 25 – HSRAMLP Interrupt Flag for SLAVE HSRAMLP
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 24 – L2HBRIDGES Interrupt Flag for SLAVE L2HBRIDGES
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 23 – LPRAMDMAC Interrupt Flag for SLAVE LPRAMDMAC
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 22 – LPRAMPICOP Interrupt Flag for SLAVE LPRAMPICOP
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 21 – LPRAMHS Interrupt Flag for SLAVE LPRAMHS
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 19 – HPB4 Interrupt Flag for SLAVE HPB4
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 18 – HPB3 Interrupt Flag for SLAVE HPB3
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 17 – HPB2 Interrupt Flag for SLAVE HPB2
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 16 – HPB0 Interrupt Flag for SLAVE HPB0
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 4 – H2LBRIDGES Interrupt Flag for SLAVE H2LBRIDGES
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 3 – HPB1 Interrupt Flag for SLAVE HPB1
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 2 – HSRAMDSU Interrupt Flag for SLAVE HSRAMDSU
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 1 – HSRAMCM0P Interrupt Flag for SLAVE HSRAMCM0P
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 0 – FLASH Interrupt Flag for SLAVE FLASH
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.