20.6.3.3 Sleep Mode Controller
A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the Sleep mode.
Mode | Mode Entry | Wake-Up Sources |
---|---|---|
IDLE | SLEEPCFG.SLEEPMODE = IDLE _n | Synchronous (2) (APB, AHB), asynchronous (1) |
STANDBY | SLEEPCFG.SLEEPMODE = STANDBY | Synchronous(3), Asynchronous |
BACKUP | SLEEPCFG.SLEEPMODE = BACKUP | Backup reset detected by the RSTC |
OFF | SLEEPCFG.SLEEPMODE = OFF | External Reset |
- Asynchronous: interrupt generated on generic clock, external clock, or external event.
- Synchronous: interrupt generated on the APB clock.
- Synchronous interrupt only for peripherals configured to run in standby.
The sleep modes (idle, standby, backup, and off) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Refer to Power Domain Controller for the power domain gating effect.
Mode | Main clock | CPU | AHBx and APBx clock | GCLK clocks | Oscillators | Regulator | NVM | |
---|---|---|---|---|---|---|---|---|
ONDEMAND = 0 | ONDEMAND = 1 | |||||||
Active | Run | Run | Run | Run(3) | Run | Run if requested | MAINVREG | Active |
IDLE | Run | Stop | Stop(1) | Run(3) | Run | Run if requested | MAINVREG | Active |
STANDBY | Stop(1) | Stop | Stop(1) | Stop(1) | Run if requested or RUNSTDBY = 1 | Run if requested | MAINVREG in low power mode | Ultra-Low power |
BACKUP | Stop | Stop | Stop | Stop | Stop | Stop | Backup regulator (ULPVREG) | OFF |
OFF | Stop | Stop | Stop | OFF | OFF | OFF | OFF | OFF |
- Running if requested by peripheral during SleepWalking.
- Running during SleepWalking.
- Following On-Demand Clock Request principle.
Idle Mode
The Idle mode allows power optimization with the fastest wake-up time.
The CPU is stopped, and peripherals are still working. As in active mode, the AHBx and APBx clocks for peripheral are still provided if requested. As the main clock source is still running, wake-up time is very fast.
- Entering Idle mode: The Idlemode is entered by executing the WFI instruction. Additionally, if the SLEEPONEXIT bit in the Arm Cortex System Control register (SCR) is set, the Idle mode will be entered when the CPU exits the lowest priority ISR (Interrupt Service Routine, refr to the "Arm Cortex" documentation for details). This mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Before entering the Idle mode, the user must select the idle Sleep Mode in the Sleep Configuration register (SLEEPCFG.SLEEPMODE = IDLE).
- Exiting Idle mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient priority to cause exception entry. The system goes back to the Active mode. The CPU and affected modules are restarted.
GCLK clocks, regulators, and RAM are not affected by the Idle sleep mode and operate in normal mode.
Standby Mode
The Standby mode is the lowest power configuration while keeping the state of the logic and the content of the RAM.
In this mode, all clocks are stopped except those configured to be running sleepwalking tasks. The clocks can also be active on request or at all times, depending on their on-demand and run-in-standby settings. Either synchronous (CLK_APBx or CLK_AHBx) or generic (GCLK_x) clocks or both can be involved in sleepwalking tasks. This is the case when for example the SERCOM RUNSTDBY bit is written to '1'.
- Entering Standby mode: This mode is entered by executing the WFI instruction after writing the Sleep Mode bit in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=STANDBY). The SLEEPONEXIT feature is also available as in Idle mode.
- Exiting Standby mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU.
Refer to Regulators, RAMs, and NVM State in Sleep Mode for the RAM state.
The regulator operates in low-power mode by default and switches automatically to the normal mode in case of a sleepwalking task requiring more power. It returns automatically to low power mode when the sleepwalking task is completed.
Backup Mode
The Backup mode allows achieving the lowest power consumption aside from OFF. The device is entirely powered off except for the backup domain. All peripherals in backup domain are allowed to run, for example, the RTC can be clocked by a 32.768 kHz oscillator. All PM registers are reset except the CTRLA.IORET bit.
- Entering Backup mode: This mode is entered by executing the WFI instruction after selecting the Backup mode by writing the Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=BACKUP).
- Exiting Backup mode: is triggered when a Backup Reset is detected by the Reset Controller (RSTC).
Off Mode
In Off mode, the device is entirely powered-off.
- Entering Off mode: This mode is entered by selecting the Off mode in the Sleep Configuration register by writing the Sleep Mode bits (SLEEPCFG.SLEEPMODE = OFF), and subsequent execution of the WFI instruction.
- Exiting Off mode: This mode is left by pulling the RESET pin low, or when a power Reset is done.