20.6.3.7 Regulators, RAMs, and NVM State in Sleep Mode

By default, in standby sleep mode and backup sleep mode, the RAMs, NVM, and regulators are automatically set in low-power mode in order to reduce power consumption:

  • The RAM is in low-power mode if its power domain is in retention or off state the device is in standby mode. Refer to RAM Automatic Low Power Mode for details.
  • Non-Volatile Memory - the NVM is located in the power domain PD2. By default, the NVM is automatically set in low power mode in these conditions:
    • When the power domain PD2 is in retention or off state.
    • When the device is in standby sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral.
    • When the device is in idle sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral.
  • Regulators: by default, in standby sleep mode, the PM analyzes the device activity to use either the main or the low-power voltage regulator to supply the VDDCORE. Refer to Regulator Automatic Low Power Mode section for details.

GCLK clocks, regulators and RAM are not affected in idle sleep mode and will operate as normal.

Table 20-4. Regulators, RAMs, and NVM state in Sleep Mode
Sleep

Mode

Switchable Power DomainsRAMs mode(1)NVMRegulators
PD0PD1PD2LP SRAMSRAMVDDCOREVDDBU
mainulp
Activeactiveactiveactivenormalnormalnormalononon
Idleactiveactiveactivenormalauto(2)onononon
Standby - case 1activeactiveactivenormalnormalauto(2)auto(3)onon
Standby - case 2activeactiveretentionnormallow powerlow powerauto(3)onon
Standby - case 3activeretentionretentionlow powerlow powerlow powerauto(3)onon
Standby - case 4retentionretentionretentionlow powerlow powerlow poweroffonon
Backupoffoffoffoffoffoffoffoffon
OFFoffoffoffoffoffoffoffoffoff
Note:
  1. RAMs mode by default: STDBYCFG.BBIAS bits are set to their default value.
  2. auto: by default, NVM is in low-power mode if not accessed.
  3. auto: by default, the main voltage regulator is on if GCLK, APBx, or AHBx clock is running during SleepWalking.
  4. For a description of the cases, see Power Domain Controller.