39.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure

The DMA Channel Descriptor (DSCR) must be aligned on a 64-bit boundary.

The DMA Channel Descriptor structure contains three fields:

• DSCR.CHXADDR: Frame Buffer base address register
• DSCR.CHXCTRL: Transfer Control register
• DSCR.CHXNEXT: Next Descriptor Address register

  Table 39-2. DMA Channel Descriptor Structure

  System Memory	Structure Field for Channel CHX
  DSCR + 0x0	ADDR
  DSCR + 0x4	CTRL
  DSCR + 0x8	NEXT