39.6.2.6 DMA Address Alignment Requirements

When programming the DSCR.CHXADDR field of the DSCR structure, the following requirement must be met.

Table 39-3. DMA Address Alignment when CLUT Mode is Selected
CLUT Mode DMA Address Alignment
1 bpp 8 bits
2 bpp 8 bits
4 bpp 8 bits
8 bpp 8 bits
Table 39-4. DMA Address Alignment when RGB Mode is Selected
RGB Mode DMA Address Alignment
12 bpp RGB 444 16 bits
16 bpp ARGB 4444 16 bits
16 bpp RGBA 4444 16 bits
16 bpp RGB 565 16 bits
16 bpp TRGB 1555 16 bits
18 bpp RGB 666 32 bits
18 bpp RGB 666 PACKED 8 bits
19 bpp TRGB 1666 32 bits
19 bpp TRGB 1666 8 bits
24 bpp RGB 888 32 bits
24 bpp RGB 888 PACKED 8 bits
25 bpp TRGB 1888 32 bits
32 bpp ARGB 8888 32 bits
32 bpp RGBA 8888 32 bits
Table 39-5. DMA Address Alignment when YUV Mode is Selected
YUV Mode DMA Address Alignment
32 bpp AYCrCb 32 bits
16 bpp YCrCb 4:2:2 32 bits
16 bpp semiplanar YCrCb 4:2:2 Y 8 bits
CrCb 16 bits
16 bpp planar YCrCb 4:2:2 Y 8 bits
Cr 8 bits
Cb 8 bits
12 bpp YCrCb 4:2:0 Y 8 bits
CrCb 16 bits
12 bpp YCrCb 4:2:0 Y 8 bits
Cr 8 bits
Cb 8 bits