20.3.13 HRAMC L2CC Register
This register is used to configure the L2 cache to be used as an internal SRAM.
| Name: | SFR_L2CC_HRAMC |
| Offset: | 0x58 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRAM_SEL | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – SRAM_SEL SRAM Selector
| Value | Description |
|---|---|
| 0 | Selects SRAM. |
| 1 | Selects L2CC. |