37.20.36 Timings Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

Name: HSMC_TIMINGSx
Offset: 0x070C + x*0x14 [x=0..3]
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 NFSEL   TWB[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 2322212019181716 
     TRR[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
    OCMSTAR[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
 TADL[3:0]TCLR[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – NFSEL NAND Flash Selection

If this bit is set to one, the chip select is assigned to NAND Flash write enable and read enable lines drive the Error Correcting Code module.

Bits 27:24 – TWB[3:0] WEN High to REN to Busy

Write Enable rising edge to Ready/Busy falling edge timing.

Write Enable to Read/Busy = (TWB[3] * 64) + TWB[2:0] clock cycles.

Bits 19:16 – TRR[3:0] Ready to REN Low Delay

Ready/Busy signal to Read Enable falling edge timing.

Read to REN = (TRR[3] * 64) + TRR[2:0] clock cycles.

Bit 12 – OCMS Off Chip Memory Scrambling Enable

When set to one, the memory scrambling is activated. (Value must be zero if external memory is NAND Flash and NFC is used).

Bits 11:8 – TAR[3:0] ALE to REN Low Delay

Address Latch Enable falling edge to Read Enable falling edge timing.

Address Latch Enable to Read Enable = (TAR[3] * 64) + TAR[2:0] clock cycles.

Bits 7:4 – TADL[3:0] ALE to Data Start

Last address latch cycle to the first rising edge of WEN for data input.

Last address latch to first rising edge of WEN = (TADL[3] * 64) + TADL[2:0] clock cycles.

Bits 3:0 – TCLR[3:0] CLE to REN Low Delay

Command Latch Enable falling edge to Read Enable falling edge timing.

Latch Enable Falling to Read Enable Falling = (TCLR[3] * 64) + TCLR[2:0] clock cycles.