34.5 Maximum Clock Frequencies
| Symbol | Description | Conditions | Max. | Units | |
|---|---|---|---|---|---|
| fGCLKGEN0/fGCLK_MAIN | GCLK Generator Output Frequency | Undivided | 48 | MHz | |
| fGCLKGEN1 | |||||
| fGCLKGEN2 | |||||
| fGCLKGEN3 | Divided | 32 | |||
| fGCLKGEN4 | |||||
| fGCLKGEN5 | |||||
| fGCLKGEN6 | |||||
| fGCLKGEN7 | |||||
| Symbol | Description | Max. | Units |
|---|---|---|---|
| fCPU | CPU clock frequency | 32 | MHz |
| fAHB | AHB clock frequency | 32 | MHz |
| fAPBA | APBA clock frequency | 32 | MHz |
| fAPBB | APBB clock frequency | 32 | MHz |
| fAPBC | APBC clock frequency | 32 | MHz |
| fGCLK_DFLL48M_REF | DFLL48M Reference clock frequency | 33 | kHz |
| fGCLK_WDT | WDT input clock frequency | 48 | MHz |
| fGCLK_RTC | RTC input clock frequency | 48 | MHz |
| fGCLK_EIC | EIC input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_0 | EVSYS channel 0 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_1 | EVSYS channel 1 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_2 | EVSYS channel 2 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_3 | EVSYS channel 3 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_4 | EVSYS channel 4 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_5 | EVSYS channel 5 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_6 | EVSYS channel 6 input clock frequency | 48 | MHz |
| fGCLK_EVSYS_CHANNEL_7 | EVSYS channel 7 input clock frequency | 48 | MHz |
| fGCLK_SERCOMx_SLOW | Common SERCOM slow input clock frequency | 48 | MHz |
| fGCLK_SERCOM0_CORE | SERCOM0 input clock frequency | 48 | MHz |
| fGCLK_SERCOM1_CORE | SERCOM1 input clock frequency | 48 | MHz |
| fGCLK_SERCOM2_CORE | SERCOM2 input clock frequency | 48 | MHz |
| fGCLK_SERCOM3_CORE | SERCOM3 input clock frequency | 48 | MHz |
| fGCLK_SERCOM4_CORE | SERCOM4 input clock frequency | 48 | MHz |
| fGCLK_SERCOM5_CORE | SERCOM5 input clock frequency | 48 | MHz |
| fGCLK_TC0, GCLK_TC1 | TC0, TC1 input clock frequency | 48 | MHz |
| fGCLK_TC2, GCLK_TC3 | TC2, TC3 input clock frequency | 48 | MHz |
| fGCLK_TC4, GCLK_TC5 | TC4, TC5 input clock frequency | 48 | MHz |
| fGCLK_TC6, GCLK_TC7 | TC6, TC7 input clock frequency | 48 | MHz |
| fGCLK_ADC | ADC input clock frequency | 48 | MHz |
| fGCLK_AC_DIG | AC digital input clock frequency | 48 | MHz |
| fGCLK_AC_ANA | AC analog input clock frequency | 48 | MHz |
| fGCLK_DAC | DAC input clock frequency | 48 | MHz |
| fGCLK_PTC | PTC input clock frequency | 48 | MHz |
Note:
- These values are based on simulation and not covered by production test limits or characterization.