PIC18F26/45/46Q10

6.6.2 CLKRCLK

Clock Reference Clock Selection MUX

Name:	CLKRCLK
Address:	0xF3A


Bit	7	6	5	4	3	2	1	0
					CLK[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CLK[3:0] CLKR Clock Selection bits

Table 6-1. CLKR Clock Sources
CLK	Clock Source
`1111`	LC8_out
`1110`	LC7_out
`1101`	LC6_out
`1100`	LC5_out
`1011`	LC4_out
`1010`	LC3_out
`1001`	LC2_out
`1000`	LC1_out
`0111`-`0101`	0101
`0100`	SOSC
`0011`	MFINTOSC (500 kHz)
`0010`	LFINTOSC (31 kHz)
`0001`	HFINTOSC
`0000`	F_OSC

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