11.8.5 STATUS

Status Register
Note:
  1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.
  2. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the Source register.
Name: STATUS
Address: 0xFD8

Bit 76543210 
  TOPDNOVZDCC 
Access RRR/WR/WR/WR/WR/W 
Reset 1100000 

Bit 6 – TO Time-Out bit

Reset States: 
POR/BOR = 1
All Other Resets = q
ValueDescription
1 Set at power-up or by execution of CLRWDT or SLEEP instruction
0 A WDT time-out occurred

Bit 5 – PD Power-Down bit

Reset States: 
POR/BOR = 1
All Other Resets = q
ValueDescription
1 Set at power-up or by execution of CLRWDT instruction
0 Cleared by execution of the SLEEP instruction

Bit 4 – N Negative bit

Used for signed arithmetic (two’s complement); indicates if the result is negative (ALU MSb = 1).
Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 The result is negative
0 The result is positive

Bit 3 – OV Overflow bit

Used for signed arithmetic (two’s complement); indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state.
Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 Overflow occurred for current signed arithmetic operation
0 No overflow occurred

Bit 2 – Z Zero bit

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 The result of an arithmetic or logic operation is zero
0 The result of an arithmetic or logic operation is not zero

Bit 1 – DC Digit Carry/Borrow bit

ADDWF, ADDLW, SUBLW, SUBWF instructions(1)
Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 A carry-out from the 4th low-order bit of the result occurred
0 No carry-out from the 4th low-order bit of the result

Bit 0 – C Carry/Borrow bit

ADDWF, ADDLW, SUBLW, SUBWF instructions(1,2)
Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 A carry-out from the Most Significant bit of the result occurred
0 No carry-out from the Most Significant bit of the result occurred
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the Source register.