16.5.2 Channel n Generator Selection

Each channel can be connected to one event generator. Not all generators can be connected to all channels. Refer to the table below to see which generator sources can be routed onto each channel and the generator value to be written to EVSYS.CHANNELn to achieve this routing. Writing the value 0x00 to EVSYS.CHANNELn turns the channel off.

Refer to the Peripheral Overview section for the available number of Event System channels.

Name:	CHANNELn
Offset:	0x10 + n*0x01 [n=0..5]
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	CHANNELn[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – CHANNELn[7:0] Channel Generator Selection

The specific generator name corresponding to each bit group configuration is given by combining Peripheral and Output from the table below in the following way: PERIPHERAL_OUTPUT.

Table 16-5. Event Generators
GENERATOR			Async/Sync	Description	Channel Availability
Value	Name
Value	Peripheral	Output
0x01	UPDI	SYNCH	Sync	Rising edge of SYNCH character detection	All channels
0x06	RTC	OVF	Async	Counter overflow	All channels
0x07		CMP		Compare match
0x08		EVGEN0		Selectable prescaled RTC event
0x09		EVGEN1		Selectable prescaled RTC event
0x10	CCL	LUT0	Async	LUT output level	All channels
0x11		LUT1
0x12		LUT2
0x13		LUT3
0x20	AC0	OUT	Async	Comparator output level	All channels
0x24	ADC0	RESRDY	Sync	Result ready	All channels
0x25		SAMPRDY		Sample ready
0x26		WCMP		Window compare
0x40	PORTA⁽¹⁾	EVGEN0	Async	Pin level ⁽²⁾	All channels
0x41	PORTA⁽¹⁾	EVGEN1	Async	Pin level ⁽²⁾	All channels
0x44	PORTC⁽¹⁾	EVGEN0	Async	Pin level ⁽²⁾	All channels
0x45	PORTC⁽¹⁾	EVGEN1	Async	Pin level ⁽²⁾	All channels
0x46	PORTD⁽¹⁾	EVGEN0	Async	Pin level ⁽²⁾	All channels
0x47	PORTD⁽¹⁾	EVGEN1	Async	Pin level ⁽²⁾	All channels
0x4A	PORTF⁽¹⁾	EVGEN0	Async	Pin level ⁽²⁾	All channels
0x4B	PORTF⁽¹⁾	EVGEN1	Async	Pin level ⁽²⁾	All channels
0x60	USART0	XCK	Sync	Clock signal in SPI Host mode and synchronous USART Host mode	All channels
0x61	USART1	XCK	Sync		All channels
0x68	SPI0	SCK	Sync	SPI server clock signal	All channels
0x80	TCA0	OVF_LUNF	Sync	Overflow/Low-byte timer underflow	All channels
0x81		HUNF		High-byte timer underflow
0x84		CMP0_LCMP0		Compare channel 0 match/Low-byte timer compare channel 0 match
0x85		CMP1_LCMP1		Compare channel 1 match/Low-byte timer compare channel 1 match
0x86		CMP2_LCMP2		Compare channel 2 match/Low-byte timer compare channel 2 match
0xA0	TCB0	CAPT	Sync	CAPT Interrupt flag set(3)	All channels
0xA1	TCB0	OVF	Sync	Counter overflow	All channels
0xA2	TCB1	CAPT	Sync	CAPT Interrupt flag set⁽³⁾	All channels
0xA3	TCB1	OVF	Sync	Counter overflow	All channels
0xC0	USB0	SETUP	Sync	SETUP received	All channels
0xC1		SOF		SOF token received
0xC2		CRC		CRC error
0xC3		UNFOVF		USB under- or overflow
0xC4		RX		Data byte received
0xC5		TX		Data byte transmitted

Note:

Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture section for details.
Event from PORT pin will be zero if input driver is disabled.
The operational mode of the timer decides when the CAPT flag is raised. Refer to the TCB section for details.