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AVR64DU28/32 Preliminary Data Sheet

AVR64DU28 AVR64DU32

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29 CRCSCAN - Cyclic Redundancy Check Memory Scan
29.2 Overview
29.2.1 Block Diagram

Introduction
Features
AVR® DU Family Overview
Security Concept
1 Block Diagram
2 Pinout
3 I/O Multiplexing and Considerations
4 Conventions
5 Hardware Guidelines
6 Power Supply
7 AVR® CPU
8 Memories
9 Peripherals and Architecture
10 GPR - General Purpose Registers
11 NVMCTRL - Nonvolatile Memory Controller
12 CLKCTRL - Clock Controller
13 SLPCTRL - Sleep Controller
14 RSTCTRL - Reset Controller
15 CPUINT - CPU Interrupt Controller
16 EVSYS - Event System
17 PORTMUX - Port Multiplexer
18 PORT - I/O Pin Configuration
19 BOD - Brown-out Detector
20 VREF - Voltage Reference
21 WDT - Watchdog Timer
22 RTC - Real-Time Counter
23 TCA - 16-bit Timer/Counter Type A
24 TCB - 16-Bit Timer/Counter Type B
25 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
26 SPI - Serial Peripheral Interface
27 TWI - Two-Wire Interface
28 USB - Universal Serial Bus Device Controller
29 CRCSCAN - Cyclic Redundancy Check Memory Scan
30 CCL - Configurable Custom Logic
31 AC - Analog Comparator
32 ADC - Analog-to-Digital Converter
33 UPDI - Unified Program and Debug Interface
34 Instruction Set Summary
35 Ordering Information
36 Package Drawings
37 Electrical Characteristics
38 Characteristics Graphs
39 Data Sheet Revision History
Microchip Information

29.2.1 Block Diagram

Figure 29-1. Cyclic Redundancy Check Block Diagram

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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