34.4.7 APMPERS2
Note:
- Refer to the 'Operation with ADC' section for more information.
| Name: | APMPERS2 |
| Offset: | 0x1F59 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VREFLP | VREFLPDAC | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ZCD | CMPLP1 | CMP1 | DAC2 | DAC1 | OPA1 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TEMP | ADCA | ADCD | FVR2 | FVR1 | BG | POSC | SOSC | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 23 – VREFLP Low-Power Voltage Reference Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of the VREFLP Peripheral Enabled |
| 0 | APM Control of the VREFLP Peripheral Disabled |
Bit 22 – VREFLPDAC Low-Power DAC Voltage Reference Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of the VREFLPDAC Peripheral Enabled |
| 0 | APM Control of the VREFLPDAC Peripheral Disabled |
Bit 15 – ZCD Zero-Cross Detect Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of ZCD Peripheral Enabled |
| 0 | APM Control of ZCD Peripheral Disabled |
Bit 14 – CMPLP1 Low Power Comparator 1 Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of CMPLP1 Peripheral Enabled |
| 0 | APM Control of CMPLP1 Peripheral Disabled |
Bit 13 – CMP1 Comparator 1 Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of CMP1 Peripheral Enabled |
| 0 | APM Control of CMP1 Peripheral Disabled |
Bit 11 – DAC2 Digital-to-Analog Converter 2 Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of DAC2 Peripheral Enabled |
| 0 | APM Control of DAC2 Peripheral Disabled |
Bit 10 – DAC1 Digital-to-Analog Converter 1 Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of DAC1 Peripheral Enabled |
| 0 | APM Control of DAC1 Peripheral Disabled |
Bit 8 – OPA1 Operational Amplifier 1 Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of OPA1 Peripheral Enabled |
| 0 | APM Control of OPA1 Peripheral Disabled |
Bit 7 – TEMP Temperature Indicator Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of Temperature Indicator Peripheral Enabled |
| 0 | APM Control of Temperature Indicator Peripheral Disabled |
Bit 6 – ADCA Analog-to-Digital Converter Peripheral Start 2(1)
| Value | Description |
|---|---|
| 1 | APM Control of ADC Peripheral Enabled |
| 0 | APM Control of ADC Peripheral Disabled |
Bit 5 – ADCD Analog-to-Digital Converter Conversion Trigger Start 2(1)
| Value | Description |
|---|---|
| 1 | APM Control of ADC Conversion Trigger Enabled |
| 0 | APM Control of ADC Conversion Trigger Disabled |
Bit 4 – FVR2 Fixed Voltage Reference 2 Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of FVR2 Peripheral Enabled |
| 0 | APM Control of FVR2 Peripheral Disabled |
Bit 3 – FVR1 Fixed Voltage Reference 1 Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of FVR1 Peripheral Enabled |
| 0 | APM Control of FVR1 Peripheral Disabled |
Bit 2 – BG Band Gap Reference Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of BG Peripheral Enabled |
| 0 | APM Control of BG Peripheral Disabled |
Bit 1 – POSC Primary Oscillator Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of Primary Oscillator Peripheral Enabled |
| 0 | APM Control of Primary Oscillator Peripheral Disabled |
Bit 0 – SOSC Secondary Oscillator Peripheral Start 2
| Value | Description |
|---|---|
| 1 | APM Control of Secondary Oscillator Peripheral Enabled |
| 0 | APM Control of Secondary Oscillator Peripheral Disabled |