23.5.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: Enable-protected

Bit 76543210 
  CLKSEL[1:0]CNTPRES[1:0]SYNCPRES[1:0]ENABLE 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 6:5 – CLKSEL[1:0] Clock Select

The Clock Select bit field selects the clock source of the TCD clock.

ValueNameDescription
0x0OSCHFInternal High-Frequency Oscillator
0x1PLLPLL
0x2EXTCLKExternal clock
0x3CLK_PERPeripheral clock

Bits 4:3 – CNTPRES[1:0] Counter Prescaler

The Counter Prescaler bit field selects the division factor of the TCD counter clock.

ValueNameDescription
0x0DIV1Division factor 1
0x1DIV4Division factor 4
0x2DIV32Division factor 32
0x3-Reserved

Bits 2:1 – SYNCPRES[1:0] Synchronization Prescaler

The Synchronization Prescaler bit field selects the division factor of the TCD clock.

ValueNameDescription
0x0DIV1Division factor 1
0x1DIV2Division factor 2
0x2DIV4Division factor 4
0x3DIV8Division factor 8

Bit 0 – ENABLE Enable

When writing to this bit, it will automatically be synchronized to the TCD clock domain.

This bit can be changed as long as the synchronization of this bit is not ongoing. See the Enable Ready (ENRDY) bit in the Status (TCDn.STATUS) register.

This bit is not enable-protected.

ValueNameDescription
0NOThe TCD is disabled
1YESThe TCD is enabled and running