3 Design Overview

The following figure shows the high-level block diagram of the reference design.

Figure 3-1. High-level Block Diagram

The camera generates a live Full HD (FHD) video (1920x1080 picture resolution) to the Bayer Interpolation IP. The FPGA fabric receives these frames and performs processing as follows:

  • IMX334 top block contains MIPI CSI2 Rx IP to get the camera data, which is passed to the Bayer Interpolation IP. Bayer Interpolation IP block converts each Bayer frame to RGB data frame. Specifically, each single 8-bit Bayer pixel data is converted to a 24-bit RGB pixel data. 
  • The 24-bit RGB pixel data is then passed through Image Processing IP's to add features like auto-brightness, R/G/B gains, contrast and so on.
  • The On Screen Display (OSD) logic injects the text "COMPRESSION RATIO x" into the image frame, where x is the value of compression ratio input from software. Each character size is 16x16 pixels. The text characters and digits in 16x16 pixel format are stored in the ROM. The OSD logic injects the text at the location specified by the coordinates input from software. The text color can also be controlled by using the color input of OSD logic. The OSD logic takes RGB as the input frame format and gives RGB frame with the injected text in the specified coordinates as the output.
  • RGB data is converted to YUV422 format using RGB to YUV convert IP.
  • 1920x1080 image is scaled down to the selected resolution using Image Scaler IP and sent to H.264 Encoder IP. The resolution can be changed from the user application through GUI interface.
  • The H.264 compressed data is written to the LPDDR memory through FIC1 AXI slave interface.
  • Application running on MSS reads the compressed data from the LPDDR4 memory.
  • On Linux, Fast Forward MPEG (FFMPEG) reads FIFO data and generates RTP packets to send over GEM.

RGB Gains, Compression quality factor, Compression Resolution, Contrast, Brightness, and so on are controlled by MSS through FIC3 Master interface.