7.3.2 Two-Wire JTAG Debug Interface

The IS2083BM devices provide a two-wire JTAG interface for SDK debugging (see the following figure). The target device must be powered, and all required signals must be connected. In addition, the interface must be enabled through a special initialization sequence (see Enabling Debugging Interface).

Figure 7-5. Two-Wire ICSP Interface

The two-wire ICSP port is used as an interface to connect a Debugger in the IS2083BM device. The following table provides the required pin connections. This interface uses the following two communication lines to transfer data to and from the IS2083BM device being programmed:

  • Serial Program Clock (TCK_CPU)
  • Serial Program Data (TDI_CPU)

These signals are described in the following two sections. Refer to the specific device data sheet for the connection of the signals to the chip pins. The following table describes the two-wire interface pins.

Table 7-2. Two-Wire Interface Pin Description
Pin NamePin TypeDescription
RST_NIReset pin
VDD_IO, ADAP_IN, BAT_INPPower supply pins
GNDPGround pin
TCK_CPUISerial Clock
TDI_CPUI/OSerial Data
Note: For more details, refer to the IS2083 SDK Debugger User's Guide available in the SDK package.

Serial Program Clock

The Serial Program Clock (TCK_CPU) is the clock that controls the updating of the TAP controller and the shifting of data through the Instruction or selected data registers. TCK_CPU is independent of the processor clock with respect to both frequency and phase.

Serial Program Data

Serial Program Data (TDI_CPU) is the data input/output to the instruction or selected data registers. In addition, it is the control signal for the TAP controller. This signal is sampled on the falling edge of TDI_CPU for some TAP controller states.