7.3.3 Enabling Debugging Interface

On the IS2083BM, debugging interfaces are enabled using the standard Microchip test patterns. Once RST_N is asserted (low), the user may provide an entry sequence on any TSTC2ENTRY and TSTD2ENTRY pin pair on the device. Once RST_N is de-asserted (high), the corresponding debugging interface is enabled as per the entry sequence.

The TSTC2ENTRY/TSTD2ENTRY pin pairs are mapped on top of the CPU JTAG interface so that two-wire debug interface may be enabled by controlling only 3 device pins (RST_N and 2 entry pins).

The Debugging mode entry sequence for the Two-Wire mode is shown in the following table, and the timing diagram is shown in the following figure.

Table 7-3. CPU Debugging Mode Entry
Debug Mode Entry SequenceMode
4D43 4851 “MCHQ”Two-Wire Debug mode
Figure 7-6. Two-Wire Debug Mode Entry